View STV0196B_1256656.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

STV0196B qpsk/bpsk demodulator and fec ic september 1996 pqfp64 (plastic package) order code : STV0196B front-end interface . i and q 6 bits digital inputs at 2fs . qpsk demodulation (two modes : a and b) . input symbol frequency (fs) up to 30msymbols/s . digital nyquist root filter : roll-off value of 0.35 in mode a . digital carrier loop : - on-chip derotator and tracking loop - carrier offset indicator - lock detector - c/n indicator for dish positioning . digital timing recovery : - internal timing error evaluation and filter - output control signal for a 2fs external vco or vcxo . digital agc : - internal signal power estimation and filter - output control signal for agc (1 bit pulse density modulation) forward error correction . inner decoder : - viterbi soft decoder for convolu- tional codes, constraint length m = 7, rate 1/2 - punctured codes 1/2, 2/3, 3/4, 5/6 and 7/8 in mode a - automatic or manual rate and phase recognition . deinterleaver : - word synchro extraction - convolutive deinterleaver . outer decoder : - in mode a : reed-solomon decoder for 16 parity bytes ; correction of up to 8 byte errors - block lengths : 204 in mode a - energy dispersal descrambler control . i 2 c serial bus description designed for the fast growing direct broadcast satellite (dbs) digital tv receiver market, the sgs-thomson STV0196B digital satellite receiver front-end integrates all the functions needed to demodulate incoming digital satellite tv signals from the tuner : nyquist filters, qpsk/bpsk demodulator, signal power estimator, automatic gain control, viterbi decoder, deinterleaver, reed- solomon decoder and energy dispersal descram- bler. this high level of integration greatly reduces the package count and cost of a set top box. the demodulator blocks are suitable for a wide range of symbol rates while the advanced error correction functions guarantee a low error rate even with small receiver antennas or low power transmitters. the STV0196B has multistandard capability. it is fully compliant with the recently defined digital video broadcasting (dvb) standard (already adopted by satellite tv operators in the usa, europe and asia) and also compatible with the main consumer digital satellite tv standards in use. 1/23
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 test v ss v dd test test test test test test test v ss v ss v ss v dd v dd v dd v dd v ss v ss v ss v dd v dd m_c lk mode clkrec agc sda scl nres d60 error d/p test test v ss v dd q0 q1 q2 q3 q4 q5 i0 i1 i2 i3 i4 i5 v ss v dd test test d0 d1 d2 d3 d4 d5 d6 d7 v ss v dd ck_out str_out 0196b-01.eps pin connections STV0196B 2/23
pin list pin number pin name type pin description signal inputs 51, 52, 53, 54, 55, 56 i [5..0] i in phase component, at twice the symbol frequency (2fs). 57, 58, 59, 60, 61, 62 q [5..0] i in quadrature component, at twice the symbol frequency (2fs). 48 m_clk i master clock input, 2fs. sampling clock of the external a to d converters. front end controls 46 clkrec o 1 bit control signal for the external clk vco. it must be low-pass filtered. 44 agc o 1 bit control signal for the external agc. it must be low-pass filtered. 35 d60 o m_clk divided by 60 signal outputs 26, 25, 24, 23, 22, 21, 20, 19 d [7..0] o output data 29 ck_out o output byte clock 30 str_out o output synchronization byte signal 33 d/p o data/parity signal 34 error o output error signal. set in case of uncorrected block. i 2 c micro interface 39 scl i serial clock 40 sda i/o serial data bus other 47 mode i 0 = mode a, 1 = mode b 1, 2, 5, 6, 13, 14, 15, 16, 17, 18, 63, 64 test o reserved for manufacturing test. it must remain unconnected 3, 7, 9, 11, 28, 32, 37, 41, 42, 49 v ss i ground references 4, 8, 10, 12, 27, 31, 38, 43, 45, 50 v dd i 3.3v supply 36 nres i negative reset 0196b-01.tbl viterbi decoder deinterleaver reed solomon decoder energy descrambler nyquist filter derotator agc lock indicator dco timing recovery carrier offset measure carrier phase tracking loop divide by 60 i 2 c bus interface agc d/p error str_out ck_out i[5...0] q[5...0] clkrec d60 m_clk scl sda mode v dd v ss d[7..0] STV0196B c/n indicator 0196b-02.eps block diagram STV0196B 3/23
functional description i-i 2 c bus specification this is the standard i 2 c protocol. the device address is o1101000o ; the first byte is therefore hex d0 for a write operation and hex d1 for a read operation. i.1 - write operation the first byte is the device address plus the direction bit (r/w = 0). the second byte contains the internal address of the first register to be accessed. the next byte is written in the internal register. the following (if any) bytes are written in successive internal registers. the transfer lasts until stop conditions are encountered. the STV0196B acknowledges every byte transfer. i.2 - read operation the address of the first register to read is programmed in a write operation without data, and terminated by stop condition. then another start is followed by the device address and r/w = 1 ; all successive bytes are now data read at successive positions starting from the initial address. the STV0196B acknowledges every byte transfer. example : write registers 0 to 3 with aa,bb,cc,dd start device address, write d0 ack internal address ack data aa ack data bb ack data cc ack stop read registers 2 and 3 start device address, write d0 ack register address 01 ack stop start device address, read d1 ack data read bb ack data read cc ack stop i.3 - identification register this read only register gives the release number of the circuit in order to ensure software compatibility. the read value is hex 83 for STV0196B and hex 81 for stv0196. internal address : hex 0b 10000011 notes : - unspecified register addresses must not be used. - all the unused bits in the registers must be programmed to 0. STV0196B 4/23
i.4 - register map functional description (continued) register hex 00 input configuration register (r/w) reset value : hex 04 0 -q(1) or q(0) input 1 signed (1) or positive (0) i & q inputs 2 nyquist filtering on (1) / off (0) 3 bpsk (1), qpsk(0) 4 to be set to 0. 5 to be set to 0. 6 to be set to 0. 7 to be set to 0. registers hex 01 to hex 05 viterbi, puncture rate thresholds (r/w) reset value : hex 20 rate hex01 vth0 0 th6 th5 th4 th3 th2 th1 th0 1/2 hex02 vth1 0 th6 th5 th4 th3 th2 th1 th0 2/3 hex03 vth2 0 th6 th5 th4 th3 th2 th1 th0 3/4 hex04 vth3 0 th6 th5 th4 th3 th2 th1 th0 5/6 hex05 vth4 0 th6 th5 th4 th3 th2 th1 th0 7/8 or 6/7 register hex 06 vsearch (viterbi) (r/w) reset value : hex 19 0 h[1..0] sync counter hysteresis value 1 2 t[1..0] sync search time out 3 4 sn[1..0] viterbi error rate averaging period. c/n indicator averaging period. 5 6 f viterbi operating status freeze (1) 7 a/m (0) automatic, (1) manual register hex 07 verror register (read only) register hex 08 vstatus register (read only) 0 pr[2..0] current puncture rate identification 1 2 3 lk (1) synchro found, (0) searching puncture rate 4 prf (1) puncture rate found, (0) searching puncture rate 5 unused set to (0) 6 unused set to (0) 7 cf (1) carrier found, (0) searching carrier register hex 09 puncture rate enable (r/w) reset value : hex 10 (mode a) 0 e0 (1) puncture 1/2 enabled, (0) disabled 1 e1 (1) puncture 2/3 enabled, (0) disabled 2 e2 (1) puncture 3/4 enabled, (0) disabled 3 e3 (1) puncture 5/6 enabled, (0) disabled 4 e4 (1) puncture7/8 (mode a), 6/7 (mode b) (0) disabled 5 unused 6 7 register hex 0a rs register (r/w) reset value : hex b8 0 rs0 (1) output clock stopped during parity, (0) continuous 1 rs1 output clock polarity 2 rs2 (1) all synchro words are hex47, (0) synchro inversion disabled 3 rs3 write error bit 4 rs4 descrambler on (1), off (0) 5 rs5 reed-solomon on (1), off (0) 6 rs6 normal operation (0), reed-solomon correction bytes to output (1) 7 rs7 de-interleaver on (1), off (0) STV0196B 5/23
functional description (continued) i.4 - register map (continued) register hex 0b identification register (read only) reset value : hex83 for STV0196B, hex 81 for stv0196 register hex 0c timing loop : time constant (r/w) reset value : hex 45 0 beta_tmg coefficient 1 2 3 4 alpha_tmg coefficient 5 6 7 istr external vco/vcxo slope polarity (0) positive, (1) negative register hex 0d timing frequency register (r/w) signed value ranging from 80 to 7f. register hex 0e carrier loop register (r/w) reset value : hex a3 0 beta_carrier coefficient 1 2 3 unused 4 alpha_carrier coefficient 5 6 7 deratator on (1), off (0) register hex 0f derotator frequency register (r/w) signed value ranging from 80 to 7f. register hex 10 carrier offset evaluator (read only) signed value ranging from 80 to 7f. register hex 11 agc control register (r/w) reset value : 18 hex. 0 agc reference level m 1 2 3 4 5 6 unused 7 iagc register hex 12 agc integrator (r/w) signed value ranging from 80 to 7f. register hex 13 agc coefficient 0 g[2..0] agc coefficient 1 2 3 unused 4 5 6 7 register hex 14 c/n indicator (read only) value ranging from 00 to ff. STV0196B 6/23
ii - adc interface ii.1 - m_clk master clock input this is the highest frequency clock of the chip, at twice the symbol frequency; all other clocks are derived from it. this clock should be output from an external vco or vcxo, controlled by clkrec output. m_clk divided by 60 is available to the system (output d60). ii.2 - i and q signal inputs those signals are coded on 6 bits, either in 2's complement or as positive values : the choice is programmable via the input configuration register. the p /2 ambiguity inherent in qpsk is solved in the error correction part. a programmable bit in a mode register allows to multiply by -1 the data on q input, in order to accommodate qpsk modulation with another con- vention of rotation sense ; (this is equivalent to a permutation of i and q inputs, or a spectral sym- metry). iii - nyquist root filter the i and q components are filtered by a digital nyquist root filter with the following features : - input : separate i and q streams, two samples per symbol. - excess bandwidth : 0.35 in mode a. - the filters may be bypassed ; in this case, the input flow is connected to the carrier and clock recovery section. input configuration register (the written value of each bit is the reset value) internal address : hex00 00000100 bpsk(1), qpsk(0) nyquist filtering on (1)/off (0) signed (1) or positive (0) i&q inputs -q(1) or q(0) input iv - timing recovery the timing loop comprises an external vco or vcxo, running at twice the symbol frequency, controlled by the output clkrec ; this signal is a pulse density modulated output, at the symbol frequency, and represents the filtered timing error. the loop is parametrised by two coefficients : al- pha_tmg and beta_tmg ; the 12 bit filter output is converted into a pulse density modulation signal which should be filtered by an analog low pass filter before commanding the vco. iv.1 - timing loop registers time constant register internal address : hex0c reset value : hex45 istr 1 0 0 0 1 0 1 invert bit alpha_tmg (1 to 6) beta_tmg (0 to 9) the bit oistro allows to change the polarity of the output signal, in order to accommodate both pos- sibilities of external vco : istr loop control 0 vco frequency raises when output average voltage raises 1 vco frequency decreases when output average voltage raises timing frequency register internal address : hex0d signed number the value of this register, when the system is locked, is an image of the frequencyoffset; it should be as close as possible to 0 in order to have a symmetric capture range ; reading it allows optimal trimming of the timing vco range. iv.2 - loop equations the external vco is controlled by the output clkrec followed by a low pass filter. the full analog swing of the output originates a relative frequency shift of 2 d f , depending on the characteristics of the external vco (typically a fraction of percent). the frequency range is therefore f = f 0 (1 d f). neglecting the analog low pass filter on the pulse modulated output, this loop may be considered as a second order loop. functional description (continued) STV0196B 7/23
the natural frequency and the damping factor may be calculated by the following formulas : f n = w n 2 p = f s 2 p ``````` ` b k 0 k d where b is programmed by the timing register : b= 2 beta_tmg . k 0 is the constant of the vco : k 0 = d f 2 26 . k d is the phase detector ; its value depends on the roll-off value and on the power of the signal. :k d = 0.977m 2 (in mode a), or k d = 0.564m 2 (in mode b). where m is the programmed reference level (see agc part), reset value : m = 24 f s is the symbol frequency, d f is the half range of the vco therefore f n = 19.2 10 - 6 ? m ? f s ? ````````` ` d f2 beta_tmg (mode a) or f n = 14.6 10 - 6 ? m ? f s ? ````````` ` d f2 beta_tmg (mode b) the damping factor is : x= a 2 ``` ` k 0 k d b with a= 2 alpha_tmg + 12 or x= 0.247 ? m ? ``` d f ? 2 alpha_tmg ```````` 2 beta_tmg (mode a) or x= 0.188 ? m ? `` ` d f ? 2 alpha_tmg ``````` 2 beta_tmg (mode b). beta_tmg can only take value from 0 to 9 ; if beta_tmg = 0, the loop becomes a first order one. alpha_tmg can take any value from 1 to 6 ; if both alpha_tmg and beta_tmg are null, the loop is open ; the duty cycle of the clkrec output is controlled by writting the timing frequency register. the next curve shows the natural frequency for a symbol frequency of 20mbd, in mode a, with nominal reference level m = 24 as a function of the vco relative frequency half range d f, for different values of the register value beta_tmg. the followingchart gives the value of the damping factor as a function of the vco relative range, for different combinations of alpha_tmg and beta_tmg, noticing that the damping factor only depends on the value of a `` b or (2 . alpha_tmg - beta_tmg ). functional description (continued) STV0196B 8/23
100 10 0.0001 0.001 0.01 res e t value be ta_tmg 9 1 1 0.1 natural frequency (khz) vco re lative fre quency ra nge ( d f) 8 7 6 5 4 3 2 0196b-03.eps figure 1 : natural frequency for fs = 20mbauds example : the vco is trimmed from 39.9mhz to 40.1mhz when the vco control output clkrec goes from duty cycle 0 to 100%. the peak-to-peak relative range is therefore 0.5% and d f = 0.0025 ; the reset values of the parameters (alpha_tmg = 4, beta_tmg = 5) leads to a natural frequency of 2.6khz, with a damping factor of 0.84. 10 1 0.1 0.0001 0.001 0.01 re se t value ksi vco relative frequency ra nge ( d f) 2alpha_tmg - beta _tmg 8 7 6 5 4 3 2 1 0 0196b-04.eps figure 2 : damping factor functional description (continued) STV0196B 9/23
v - carrier recovery ; derotator the input of the circuit is a pair of demodulated signals ; however, there may subsist some phase error not corrected by the front end loop. furthermore, the demodulation may be done at constant frequency; the tuner is trimmed in order to make the useful signal bandwidth centered on this demodulation frequency ; in that case, a carrier offset frequencymay subsist; it is fixed by the mean of the on-chip derotator which acts as a fine tuning carrier loop. the derotator frequency range is limited to an interval corresponding to f s /16. v.1 - loop parameters like the timing loop, the carrier loop is a second order system where two parameters a and b may be programmed respectively with alpha_car and beta_car. carrier loop parameter registers internal address : hex0e 10100011 derotator on/off alpha_carrier beta_carrier derotator frequency register internal address : hex0f signed number this 8 bit r/w register may be written at any time to force the central frequency of the derotator to start the carrier research, or read, when the loop is locked,in order to know the current carrier offset (one lsb correspond to f s /2048). v.2 - loop equations the natural pulsation is : w n = 10 - 3 ? f s ? ````````` ` m ? 2 beta_car and the damping factor is : x= 0.128 ? 2 alpha_car ? ````` m 2 beta_car . where m is the reference value (see agc registers). the next table gives for the nominal amplitude m = 24 the natural period (in symbols), and the damping factor for the possible values of alpha_car. as an example, the corresponding natural frequency is given assuming a symbol frequency of 20mbauds. the shaded area correspond to the reset values. beta_car (reg. value) 01 2 34567 t n =2 p / w n (symb per) na 907 642 454 321 227 160 113 f n (khz) for f = 20mbd 22 31 44 62 88 125 177 alpha_car (reg. value) damping factor 0nana na nanananana 1 na 0.89 0.63 0.44 0.31 0.22 0.16 0.11 2 na 1.77 1.25 0.89 0.63 0.44 0.31 0.22 3 na 3.54 2.51 1.77 1.25 0.89 0.63 0.44 4 na 7.09 5.01 3.54 2.51 1.77 1.25 0.89 5 na 14.18 10.03 7.09 5.01 3.54 2.51 1.77 vi - carrier offset evaluator an 8 bit register may be read at any time; it gives a signed value proportionnal to the carrier fre- quency offset according to the expression : d f = 1.8 . 10 -6 .m 2 .n.f s (in mode a) where f s is the symbol frequency, m the symbol module (agc reference), n the read value. the maximum value for n is reached in nominal conditions for a carrier offset of 16% of f s ;if greater, n remains saturated, giving a reliable sign indication over more than 50% f s range. carrier offset register internal address : hex10 signed number vi.1 - lock indicator this 1 bit carrier found flag may be read (see viterbi status register) at any time ; it indicates that a qpsk signal is found, and that the carrier loop is closed ; this flag allows to detect false lock that can happen if the loop bandwidth is small regarding the frequency offset. vii - carrier to noise indicator internal address : hex14. read only register. b7 b6 b5 b4 b3 b2 b1 b0 this register can be used to estimate the carrier to noise level (eb/no) in a range from 4 to 16db. the register value dependson both the agc refer- ence level omo (see paragraph viii) and the control bits osn[1..0]o (see paragraph ix). for more details about how to use this register, please refer to the annexe 1. functional description (continued) STV0196B 10/23
viii - agc control the modulusof the input is compared to a program- mable threshold; the difference is scaled by the agc coefficient, then integrated; the result is con- verted into a pulse density modulation signal to drive the agc output ; it may be filtered by a simple analogue filter to control the gain command of any amplifier before the a to d converter. the 8 integrator msb's may be read or written at any time by the micro; when written, the lsb's are reset. the integrator value is the level of the agc output, after low pass filtering ; it gives an image of the input signal power, whatever this signal is, and can be used to point the antenna. the coefficient may be reset by programmation; in that case, the agc reduces to a programmable voltage synthesiser. the agc reference level omo value impacts the value of the following functions : - carrier to noise indicator (see paragraph vii) - the carrier loop (see paragraph v.2) - the timing loop (paragraph iv.2) - carrier offset evaluator (paragraph vi) control registers internal addresses : hex11 iagc 0 0 1 1 0 0 0 invert signal reserved agc reference level (omo) internal addresses : hex12 agc integrator value (signed) (read/write register) internal addresses : hex13 00000010 reserved g[2..0] : agc coefficient the 8 bit signed value in the integrator is the image of the agc output; reading this value gives an image of the rf signal power. a constant error on the modulus leads to a ramp at the output of the integrator with value : agc_int = 2 agc_coeff-16 . error as a consequence, for the reset conditions, a con- stant signal of null value (error = 24) should cause the output agc duty cycle to go from 100% to 0% in 2 22 symbol periods, or 8.7ms at 20mbauds. if iagc is set, the sign of the integrator is inverted. ix - viterbi decoder and synchronization the convolutives codes are generated by the polynoms gx = 171 oct and gy = 133 oct . the viterbi decoder computes for each symbol the metrics of the four possible paths, proportional to the square of the euclidian distance between the received i and q and the theoretical symbol value. the puncture rate and phase are estimated on the error rate basis. five rates are allowed and may be enabled/dis- abled through register programming : 1/2, 2/3, 3/4,5/6, 7/8. in mode b, 7/8 is replaced by 6/7. for each enabled rate, the current error rate is compared to a programmable threshold; if it is greater, anotherphase (or anotherrate) is tried until the good rate is obtained. a programmable hysteresis is added to avoid to loose the phase during short term perturbation. the rate may also be imposed by the external software, and the phase is incremented only on micro request ; the error rate may be read at any time in order to use other algorithm than imple- mented. the decoder is accessed via a set of 9 registers : threshold registers (vth0 to vth4) internal address : hex1 (vth0) to 5 (vth4) reset value : hex20 threshold value vth0 0 th6 th5 th4 th3 th2 th1 th0 rate 1/2 vth1 0 th6 th5 th4 th3 th2 th1 th0 rate 2/3 vth2 0 th6 th5 th4 th3 th2 th1 th0 rate 3/4 vth3 0 th6 th5 th4 th3 th2 th1 th0 rate 5/6 vth4 0 th6 th5 th4 th3 th2 th1 th0 rate 7/8 or 6/7 for each register, bits 6 to 0 represent an error rate threshold : the average number of errors happen- ing during 256 bit periods; the maximum program- mable value is 127/256 (higher error rates are of no practical use). puncture rate enable register internal address : hex09 reset value : hex10 (mode a) 0 0 0 e4e3e2e1e0 e4 : enablepuncturedrate 7/8 (mode a) or 6/7 (mode b) e3 : enable punctured rate 5/6 e2 : enable punctured rate 3/4 e1 : enable punctured rate 2/3 e0 : enable basic rate 1/2 functional description (continued) STV0196B 11/23
ix - viterbi decoder and synchronization (continued) functional description (continued) other registers vsearch internal address : hex06 a/m f sn [1..0] to [1..0] h [1..0] a/m : automatic/manual f : freeze sn [1..0] : averaging period. it gives the number of bits required to calculate the rate error : sn [1..0] number of bits 00 1.024 01 4.096 10 16.384 11 65.536 reset value : sn=01 (4096 bits) the sn[1..0] bits also inpacts the c/n indicator (see paragraph vii). to [1..0] : time out value. it programs the maximum durationof the synchro word research in automatic mode; if no sync is found within this duration, the phase is incremented. to [1..0] time out (in 1024 bit periods) 00 16 01 32 10 64 11 128 reset value : to=10 (64k bit periods). h [1..0] : hysteresis value. it programs the maximum value of the sync counter. the unit is the block duration (204 bytes in mode a). h [1..0] sync counter max value (in blocks periods) 00 forbidden value 01 32 10 64 11 128 reset value : h=01 (32 blocks). in mode a, the sync word is 47hex and it is com- plemented to b8hex for every 8th block. an up/down sync counter counts whenever a sync word is recognized with the good timing, and counts down for each missing sync word ; this counter is bounded by a programmable maximum value; when this value is reached, the lk bit (olockedo) is set in vstatus register; when the event counter counts down until 0, this flag is reset. vsearch bit 7 (a/m) and bit 6 (f) programs the automatic/manual(or computer aided) search mode : - if a/m =0 and f=0 : automatic mode; successive enabled punctured rates are tried with all possible phases, until the system is locked and the block synchro found ; this is the default (reset) mode. - if a/m=0 and f=1, the current puncture rate is frozen, if no sync is found, the phase is incre- mented, but not the rate number; this mode al- lows to shorten the recovery time in case of noisy conditions: the puncture rate is not supposed to change in a given channel. in a typical computer aided implementation, the re- search begins in automatic mode; the micro reads the error rate or the prf flag in order to detect the capture of a signal; then it switches f to 1, until a new channel is requested by the remote control. - if am=1 : manual mode; in this case, only one puncture rate should be validated, the system is forced to this rate, on the current phase, ignoring the time-out registerand theerror rate;in this mode, each 0 to 1 transition of the bit f leads to a phase incre- mentation, allowing full control of the operation by an external micro by choosing the lowest error rate : resetvalue: a/m=0, andf=0;automaticsearch mode verror (read only register) internal address : hex07 error rate at any time, the last value of the error rate may be read in this register (unlike vth, the possible range is 0 to 255/256). vstatus (read only register) internal address : hex08 cf 0 0 prf lk pr [2..0] cf : carrier found flag (see carrier recovery) cf when set, indicates that a qpsk signal is present at the input of the viterbi decoder. prf : puncture rate found prf indicates the state of the puncture rate research : 0 for searching, 1 when found ; this bit is irrelevant in manual mode. lk : locked/searchingthe sync word lk indicates the state of the sync word research : 0 for searching, 1 when found. pr [2..0] : current puncture rate it hold the current puncture rate indice with the correspondance : punctured rate regiter value pr[2..0] basic 1/2 100 punctured 2/3 000 punctured 3/4 001 punctured 5/6 010 punctured 7/8 (mode a) or 6/7 (mode b) 011 STV0196B 12/23
x - convolutional de-interleaver this is a 204 x 12 convolutional interleaver in mode a ; the periodicity of 204 bytes for sync byte is preserved. the de-interleaver may be skipped (see rs register). xi - reed-solomon decoder and descrambler the input blocks are 204 byte long with 16 parity bytes in mode a; the synchro byte is the first byte of the block. up to 8 byte errors may be fixed. code generator polynom: g(x) = (x - w 0 )(x- w 1 ) (...) (x - w 15 ) over the galois field generated by : x 8 +x 4 +x 3 +x 2 +1=0 energy dispersal descrambler : output energy dispersal descrambler generator : x 15 +x 14 +1 the polynom is initialised every eight blocks with the sequence 100101010000000. the synchro words are unscrambled. control register : rs register internal address : hex0a the reset value is written in each register cell rs7 rs6 rs5 rs4 rs3 rs2 rs1 rs0 10111000 rs7 : de-interleaver enable if 1, the input flow is deinterleaved. if 0, the flow is not affected. rs6 : if 0, output data are corrected bytes (normal operating mode). if 1, outputdata arereed-solomoncorrection bytes (error count mode) (see note 1). rs5 : reed-solomon enable if 1, the input code is corrected. if 0, no correction happens; all the data are fed to the descrambler. the error signal remains inactive. rs4 : descrambler enable if 1, the output flow from reed-solomon decoder is descrambled. if 0, the descrambler is desactived. rs3 : write error bit if rs3=1, and uncorrectible error happens, the msb of the first byte following the sync byte is forced to 1after descrambling. rs2 : super synchro suppression if rs2=1, all synchro bytes are hex47 in mode a. if rs2=0, the synchro is complemented every 8th packet. it allows, when scrambler is off, to provide rs coded signals for use in low-cost smatv interface. rs1 : output clock polarity if rs1=0, data and control signals change during high to low transition of ck_out. if rs1=1, they change during the low to high transition. rs0 : output clock configuration if rs0=0, ck_out is continuous. if rs0=1, ck_out remains low during the parity bits. note 1 : when rs6 = 1, the output data are the correction bytes applied to data incoming the reed-solomon block. the number of bits at 1 in these output data represent therefore the number of errors remaining at the output of viterbi decoder. all null output data mean no error left after viterbi decoding. remark : output datas are meaningless when error flag (pin 34) is set to high level. functional description (continued) da ta p a rity no error uncorre cte d p a cke t no error ck_out d/p str_out error rs0=0, rs1=0 rs0=1, rs1=0 rs0=0, rs1=1 rs0=1, rs1 =1 da ta p a rity da ta p a rity 0196b-05.eps figure 3 STV0196B 13/23
absolute maximum ratings maximum limits indicate where permanent device damages occur, continuous operation at these limits is not intended and should be limited to those conditions specified in section odc electrical specificationso. symbol parameter value unit v dd power supply (1) -0.3 to 4 v v i voltage on input pins (2) -0.3 to v dd + 0.3 v v o voltage on output pins -0.3 to v dd +0.3 v t stg storage temperature -40 to +150 o c t oper operating ambient temperature -10 to +85 o c p d power dissipation 1.5 w notes : 1. all v dd to be tied together 2. scl, sda, nres pins can be tied to 5v 10% with an impedance 2k w (remark in these conditions the input leakage current becomes higher than 10 m a). 0196b-02.tbl dc electrical characteristics (v dd = 3.3v, t amb =25 o c unless otherwise specified) symbol parameter test conditions min. typ. max. unit v dd operating voltage 0 o c t oper 70 o c 0 o cSTV0196B 14/23
i 2 c bus characteristics (see figure 9) symbol parameter test conditions min. typ. max. unit v il v ih input logic low voltage input logic high voltage see note 1 -0.3 2.0 0.8 5.5 v v v ol v oh output logic low voltage output logic high voltage c load = 20pf, i load = 2ma, m_clk = 60mhz, see note 1 2.4 0.5 5.5 v v i lk input leakage current v in =0vtov dd , see note 2 -10 10 m a c in input capacitance 3.5 pf i ol output sink current v ol = 0.5v 10 ma t sp pulse width of spikes which must be suppressed by the input filter 050ns f scl scl clock frequency 0 400 khz t buf bus free time between a stop and start condition 1.3 m s t hd,sta hold time (repeated) start condition. after this period, the first clock pulse is generated. 0.6 m s t low t high low period of the scl clock high period of the scl clock 1.3 0.6 m s m s t su,sta set-up time for a repeated start condition 0.6 m s t su,sto set-up time for stop condition 0.6 m s t hd,dat data hold time see note 3 0 0.9 m s t su,dat data set-up time see note 4 100 ns t r ,t f rise and fall time of both sda and scl signals see note 5 20 + 0.1 c b 300 ns c b capacitive load for each bus line 400 pf notes : 1. an impedance higher than 2k w is required when sda and scl are tied to a 5v 10% voltage line. 2. leakage current exceeds 10 m a when sda and scl are tied to a 5v 10% line. 3. a device must internally provide a hold time of at least 300ns for the sda signal (refered to the v ih min. of the scl signal) in order to bridge the undefined region of the falling edge of scl. the maximum thd,dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. 4. a fast-mode i 2 c bus device can be used in a standard-mode i 2 c bus system, but the requirement t su,dat 250ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max. +t su,dat = 1000 +250 = 1250ns (according to the standard-mode i 2 c bus specification) before the scl line is released. 5. c b = total capacitance of one bus line in pf. 0196b-03.btbl STV0196B 15/23
t high t low t m_clk 2.0v 0.8v t f t r m_clk 0196b-06.eps figure 4 t 60 d60 0196b-08.eps figure 6 m_clk i,q t su t h (v il +v ih )/2 0196b-07.eps figure 5 ck_out d[7:0], d/p . s tr_out, error t ckh t cksu 0196b-09.eps figure 7 ck_out d[7:0], d/p . str_out, error t ckh t cks u 0196b-10.eps figure 8 t buf t low t high t sp t hd,s ta t hd,dat t f t r t s u,dat t s u,s ta t s u,s to sda scl t hd,s ta 0196b-11.eps figure 9 STV0196B 16/23
v ddl v ddl v ddl v ddl v ddl v ddl 29 30 36 37 38 40 31 32 33 34 35 39 16 17 18 19 20 26 27 28 15 21 22 23 24 25 12345678910111213 51 50 49 55 54 53 52 61 60 59 58 57 62 56 63 64 14 41 42 43 44 45 46 47 48 v ddl v ddl v ddl v ddl error d/p gnd ck_out d7 str_out d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 10 11 12 13 data outputs 1 d/60 reset 1 2 3 4 5 6 7 8 9 10 16 17 18 19 20 26 27 28 11 12 13 14 15 21 22 23 24 25 s t v 0 1 9 0 r19 560 w c22 22 m f c21 100nf v ddl c20 100nf c19 22 m f c12 22 m f c13 100nf v ddl c14 100nf c15 100nf c18 100nf c17 100nf r3 68 w v dda c10 100nf c11 100nf v dda v ddl c16 100nf r4 68 w r20 10k w 5v c24 220pf c23 100nf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lm324 r30 22k w r31 8.2k w c33 1nf r27 220k w r36 8.2k w c36 1nf r32 39k w c35 1nf r34 82k w c34 100nf 20 to 28v d1 bb909 x1 40mhz r22 22k w c26 82pf c25 39pf r21 330 w r23 10k w q1 bf959 +5v r37 82k w c37 1nf sda scl 3.3k w 3.3k w +5v 100nf c2 c1 100nf c3 100nf c4 100nf c5 100nf +12v +5va c6 100nf +5va c8 100nf c7 220 m f +5va bsfr68g15 tuner 22 m f 35v 20v to 28v lnb supply & control 12v 5v 5va v ddl v dda 22 m h 12v 5v 3.3v 22 m h STV0196B v ddl c45 c42 c47 c46 v ddl c48 v ddl c43 v ddl c49 c44 v ddl c52 c50 c51 pins 4-3-10-12 pins 27-31 pins 38-43-50 i 2 c bus 74f04 r2 1k w r1 1k w q i 22 m f r18 47 w l1 1 m h 0196b-12.eps application diagram : STV0196B/stv0190fixed 20 mbauds application STV0196B 17/23
v ddl v ddl v ddl v ddl v ddl v ddl 29 30 36 37 38 40 31 32 33 34 35 39 16 17 18 19 20 26 27 28 15 21 22 23 24 25 12345678910111213 51 50 49 55 54 53 52 61 60 59 58 57 62 56 63 64 14 41 42 43 44 45 46 47 48 v ddl v ddl v ddl 1 2 3 4 5 6 7 8 9 10 16 17 18 19 20 26 27 28 11 12 13 14 15 21 22 23 24 25 s t v 0 1 9 0 c22 22 m f c21 100nf v ddl c20 100nf c19 22 m f c12 22 m f c13 100nf v ddl c14 100nf c15 100nf c18 100nf c17 100nf r3 68 w v dda c10 100nf c11 100nf v dda v ddl c16 100nf r4 68 w r2 1k w r1 1k w r20 10k w 5v c24 220pf c23 100nf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lm324 r30 1k w r31 8.2k w c33 10nf r27 220k w c36 1nf r32 39k w c35 1nf r34 82k w c34 100nf r28 22k w r29 100k w c32 1nf r26 10k w d2 d1 2 x bb909a c30 220pf c29 15pf l2 0.33 m h r22 22k w c26 82pf c25 39pf r21 330 w r23 10k w q1 bf959 r37 82k w c37 1nf 100nf c2 c1 100nf c3 100nf c4 100nf c5 100nf +12v +5va c6 100nf +5va c8 100nf c7 220 m f +5va bsfr68g15 tuner 22 m f 35v 20v to 28v lnb supply & control 12v 5v 5va v ddl v dda 22 m h 12v 5v 3.3v 22 m h STV0196B v ddl c45 c42 c47 c46 v ddl c49 v ddl c43 v ddl c48 c44 v ddl c52 c50 c51 pins 4-3-10-12 pins 27-31 pins 38-43-50 q i 74f04 22 m f r18 47 w r19 560 w r23 10 w +5v c28 100nf c27 22 m f r25 10k w c31 33nf 20 to 28v r36 8.2k w r35 1k w r33 1k w c30 2.2nf r40 22k w r41 68 w c39 22 m f c40 100nf c41 22 m f d3 5.1v r43 1k w +12v 3.3k w 3.3k w +5v v ddl tc74su04 d7 d6 d5 d4 d3 d2 d1 d0 d/60 vco adj (pwm) sda scl reset error d/p strout ckout 0196b-13.eps application diagram : STV0196B/stv0190multirate application STV0196B 18/23
the c/n indicator register permanently reports a value s which depends on the c/n level at the input of the STV0196B. the c/nindicator offers a programmable sensitivity which allows a reliable c/n estimation over a wide eb/no range (4db to 16db typically) ; this is par- ticularly useful to optimize the dish positioning. remark : in this note, we have assumed that : c n = e b n o ? 2 ( pr ) , pr : puncture rate the sensitivity of the c/n indicator is dependant on the sn bits of the register vsearch (hex06) and on the agc function reference level omo. a - suggested procedure to reliably estimate the actual c/n as no simple mathematical low ensumes a good matching between the c/n indicator and the actual c/n, the method relies on a comparaison of the value s (reported by the c/n indicator) with a reference look-up table which has been realized under well controlled conditions. basically there are 3 steps in the c/n estimation software. 1. to collect c/n indication (under adapted conditions). 2. indication scaling and correction versus the puncture rate 3. comparaison with the look-up table a.1 - to collect c/n indication the purpose of this first step is to collect the c/n indicator with the appropriate sensitivity (sn bits and agc reference level m). basically : - the value reported by the c/n indicator is propor- tional to the number of bits (at the output of the viterbi decoder) selected by the sn bits. - the agc reference level is only changed to ap- preciate the high eb/no ratios. this second pa- rameter has to be used with some care. procedure : before to make an estimation, the vstatus register (internal address hex 08) must be checked to make sure that : - a carrier is actually present (bit 7) - puncture rate is found (bit 4) - puncture rate is known (bits 0-1-2) remark : optionally, it is possible to make an estimation without informations about the puncture rate (useful when the dish is still very far from optimum position), in such case the puncture rate is forced. the c/n indicator register has no overflow detec- tion, so it is necessary to start the measure with the lowest sensitivity (sn = 00) and to gradually in- crease it (using sn bits). due to the noise, the result s of the measure may have a lot of dispersion, consequently it is recommended to measure s several times (typically 100 times) and to calculate the average value. remark : the requred duration t w between two readings of the register must be higher than : t w ( min. ) = bc br br = 2 (fs) x (pr) with bc : bit count (selected by sn bits) fs : symbol rate pr : puncture rate when the current average value of the measure s is lower than 63, the measure is done again with a higher sensitivity. with this care the new c/n measure s does not overflow the counter (the counting time is multiplied by 4 at each step). in practice some margin is given to this threshold : a higher sensitivity is selected when the average value of s is lower than 60. when the maximum sn value is reached (sn = 11 ? to 65 536 bits at the output of the viterbi decoder), the sensitivity can be further increased by lowering the agc reference level (parameter m , internal address hex11, bit 0 to bit 5). remark : there is the need to change the agc reference level only in case of high c/n conditions, then to change the reference level has no important influence on the bit error rate (ber). in other words, a completete c/n estimation can be run during the operation of the receiver. when the highest possible sensitivity is found the result s (average value) is ready for further process. annexe 1 : c/n estimation STV0196B 19/23
a.2 - scaling and correction versus puncture rate scaling this simple operation is recommended to easily compare data which have been recorded under different sensitivity conditions. to do so, the result s of the c/n indication is multiplied by a coefficient so that the scaled value would correspond to a measure done with the highest counting period (sn = 11). remark : scaling is not done for results which have beenrecorded afterchanging the agcreferencelevel. scaling operation : scaled_value = (s) x (factor) factor = 64 when c/n estimation is done with sn = 00 factor = 16 when c/n estimation is done with sn = 01 factor = 4 when c/n estimation is done with sn = 10 factor = 1 when c/n estimation is done with sn = 11 correction versus puncture rate this correction is not required when a reference look-up table have been memorized for each pos- sible puncture rate. when required, the correction is done with respect to the puncture rate prref of the reference look-up table : scorrected =( s ) ? prcurrent prref pr current : the puncture currently identified with the bits 0,1,2 of vstatus register. a.3 - comparing with the look-up table in the application the read value srs (scaled and corrected) will seldom exactly match a value of the look-up table ; consequentlythere will be the need for some interpolation. to make it simple, a linear interpolation is preferred, with such a solution a good precision can be achieved when the look-up table is built with a small step for the c/n (or eb/no). interpolation generally ssr will be between two values of the reference look-up table : v (min.) ssr v (max.) , with v (min.) corresponding c/n (max.) and v (max.) corresponding to c/n (min.) (with typically (c/n (max.) ) - (c/n (min.) ) = 0.5db). the calculated c/n corresponding to ssr is : c / n = c/n ( max. ) - ? ? c/n ( max. ) - c/n ( min. ) ? ? ? v ( min. ) - ssr v ( min. ) - v ( max. ) in above calculation c/n (or eb/no) are given in algebraic value (not in db). annexe 1 : c/n estimation (continued) STV0196B 20/23
normal process c/n estimation check vstatus sn < ----- 00 collect c/n data 100 times and calculate average value s<60 sn = 11 s<40 m < ----- m - 4 collect c/n data 100 times and calculate average value s<20 m < ----- m - 4 collect c/n data 100 times and calculate average value compare with look-up table t3 compare with look-up table t2 compare with look-up table t1 output c/n estimation sn < ----- sn + 1 scaling s correction versus puncture rate a go to tuning routine end of estimation restore agc reference level to normal value return to normal process a ny ny n y y n y n ok t1 : look-up table for normal value of m (agc reference level) t2 : look-up table for m - 4 t3 : look-up table for m - 8 0196b-17.eps b - flow chart following is a simplified flow chart. annexe 1 : c/n estimation (continued) STV0196B 21/23
c - results the results reported in the following table are typical values. when evaluating another application some differences may be especially noticed when eb/no is higher than 10db, in these conditions the charac- teristics of the tuner and the a/d converter may influence the results. conditions : puncture rate : 2/3, 20mbauds signal, dvb encoding (rs : 188/204), c/n = eb no 2 ? ( pr ) eb/no (db) measurement conditions s s scaled sn bits (hex) agc, m (dec) 4 1 20 152 2.432 4.5 137 2.192 5 121 1.936 5.5 105 1.664 6 92 1.474 6.5 78 1.248 7 64 1.024 7.5 2 20 205 820 8 168 672 8.5 131 524 9 98 392 9.5 73 292 10 3 20 212 212 10.5 146 146 11 95 95 11.5 61 61 12 3 16 122 12.5 84 13 55 13.5 35 14 22 14.5 13 15 3 12 128 15.5 95 16 70 annexe 1 : c/n estimation (continued) STV0196B 22/23
a a2 a1 b c 16 17 32 33 48 49 64 e3 d3 e1 e d1 d e 1 k b pqfp64 l l1 seating plane 0. 10mm pmpqfp64.eps package mechanical data 64 pins - plastic quad flat pack dimensions millimeters inches min. typ. max. min. typ. max. a 3.40 0.134 a1 0.25 0.010 a2 2.55 2.80 3.05 0.100 0.110 0.120 b 0.30 0.45 0.0118 0.0177 c 0.13 0.23 0.005 0.009 d 16.95 17.20 17.45 0.667 0.677 0.687 d1 13.90 14.00 14.10 0.547 0.551 0.555 d3 12.00 0.472 e 0.80 0.0315 e 16.95 17.20 17.45 0.667 0.677 0.687 e1 13.90 14.00 14.10 0.547 0.551 0.555 e3 12.00 0.472 k0 o (min.), 7 o (max.) l 0.65 0.80 0.95 0.026 0.0315 0.0374 l1 1.60 0.063 pqfp64.tbl information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1996 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. STV0196B 23/23

▲Up To Search▲

Price & Availability of STV0196B

	To Download STV0196B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .